Current things..
I got my rom board working last week (had to desolder the rom and resolder in a zif socket). Thanks to Charles for helping me out with some things 
There’s some special stuff instore for this rom board. The one I’ll make public is the 64meg mapper based on the Street Fighter 2. I call it the extend SF2 mapper 
It’ll be a series of TTL logic until I can get someone to program a PAL or GAL for me. The other project is more advanced, but you’ll just have to wait and see what it is. (Charles is awesome)
Chris Covell got pucrunch working for hucard rom projects (and fixed a bug in my code too!). This is awesome. Any real hucard project needs a serious compression scheme for tiny ram footprint project and this totally fits the bill. Pucrunch works surprisingly good with only a 256 or 512 byte buffer.
If you don’t know, Ki the author of PC2E PC-Engine emulator that Ootake is based off of, is still active in the PCE community. He’s got some serious hardware projects in the works. One of them is totally disassembled PC-Engine with each chip setup as plugin boards. He’s able to single step the whole system or clock it really slow (yes, I’m jealous). Charles and I had talked about a new method for doing the interlaced display mode on the PCE. The current method involves switching between 263 scanlines and 262 scanlines every other frame. This works great for standard definition displays and some(most?) capture cards, but it’s not a legal interlaced signal. No HDTVs (CRT or not) handle the signal correctly. There’s speculation that the VCE that generates the composite frame work/output uses a separate timing mechanism for a frames length than a scanline counter - based on a few observations from tests. IIRC, changing the register that handles this immediately ends the currently scanline - anywhere in the scanline. Ki said he should be able to take a look as this behavior at a slower rate. I’m crossing my fingers.
On a side note, the Genesis interlace mode isn’t entirely NTSC legal either. It generates a lot of half lines during vblank, but if you add all the halfs up and with the full scanlines, you get 262.5 for NTSC (which is the correct number of scanlines for interlaced mode). The interesting thing is that if those half scanlines were full (except for the last one), it would generate a PAL frame :O Speculation is that some of the internal circuitry was reused to save costs. Pretty interesting. I need to test out how my HDTV handles that interlaced signal.
Sarcie (the author of mednafen), has written a software ADPCM decoder demo for PCE. Sounds great It uses the 10bit PCM playback channel pair method for the decoded output.
There is more news, but I don’t have time to post anymore currently. Will do so in the next few days.
